Instruction Set Notes | Basic Computer Engineering | RGPV BTech First Year
Instruction Set Notes | Basic Computer Engineering | RGPV BTech First Year
Instruction Set
Instruction Set Computer Architecture рдХрд╛ рдПрдХ рдорд╣рддреНрд╡рдкреВрд░реНрдг рднрд╛рдЧ рд╣реИред CPU рдХрд┐рд╕реА рднреА рдХрд╛рд░реНрдп рдХреЛ рд╕реАрдзреЗ рдирд╣реАрдВ рд╕рдордЭрддрд╛ рдмрд▓реНрдХрд┐ рдЙрд╕реЗ Instructions рдХреЗ рд░реВрдк рдореЗрдВ Commands рджреА рдЬрд╛рддреА рд╣реИрдВред рдЗрди рд╕рднреА Commands рдХреЗ рд╕рдореВрд╣ рдХреЛ Instruction Set рдХрд╣рд╛ рдЬрд╛рддрд╛ рд╣реИред рдкреНрд░рддреНрдпреЗрдХ Processor рдХрд╛ рдЕрдкрдирд╛ Instruction Set рд╣реЛрддрд╛ рд╣реИ рдЬреЛ рдпрд╣ рдирд┐рд░реНрдзрд╛рд░рд┐рдд рдХрд░рддрд╛ рд╣реИ рдХрд┐ Processor рдХреМрди-рдХреМрди рд╕реЗ Operations Execute рдХрд░ рд╕рдХрддрд╛ рд╣реИред
Introduction
Computer Program рдЕрдиреЗрдХ Instructions рдХрд╛ рд╕рдореВрд╣ рд╣реЛрддрд╛ рд╣реИред рдЬрдм Program Execute рд╣реЛрддрд╛ рд╣реИ рддреЛ CPU рдПрдХ-рдПрдХ Instruction рдХреЛ Fetch, Decode рдФрд░ Execute рдХрд░рддрд╛ рд╣реИред Instruction Set CPU рджреНрд╡рд╛рд░рд╛ рд╕рдордЭреА рдЬрд╛рдиреЗ рд╡рд╛рд▓реА рд╕рднреА Instructions рдХрд╛ Collection рд╣реЛрддрд╛ рд╣реИред
Instruction Set Architecture (ISA) Processor рдФрд░ Software рдХреЗ рдмреАрдЪ Interface рдХрд╛ рдХрд╛рд░реНрдп рдХрд░рддреА рд╣реИред
Definition of Instruction Set
Instruction Set рдЙрди рд╕рднреА Machine Language Instructions рдХрд╛ рд╕рдореВрд╣ рд╣реИ рдЬрд┐рдиреНрд╣реЗрдВ рдХреЛрдИ Processor Execute рдХрд░ рд╕рдХрддрд╛ рд╣реИред
Instruction Set = Collection of Machine Instructions
Instruction Format
рдПрдХ Instruction рд╕рд╛рдорд╛рдиреНрдпрддрдГ рджреЛ рднрд╛рдЧреЛрдВ рд╕реЗ рдорд┐рд▓рдХрд░ рдмрдиреА рд╣реЛрддреА рд╣реИред
- Opcode (Operation Code)
- Operand
| Field | Description |
|---|---|
| Opcode | Operation to Perform |
| Operand | Data or Address |
Example: ADD R1, R2
рдпрд╣ Instruction Register R1 рдФрд░ R2 рдХреЗ Data рдХреЛ рдЬреЛрдбрд╝рддреА рд╣реИред
Types of Instructions
- Data Transfer Instructions
- Arithmetic Instructions
- Logical Instructions
- Branch Instructions
- Input Output Instructions
- Machine Control Instructions
1. Data Transfer Instructions
рдЗрди Instructions рдХрд╛ рдЙрдкрдпреЛрдЧ Data рдХреЛ рдПрдХ Location рд╕реЗ рджреВрд╕рд░реА Location рдкрд░ рднреЗрдЬрдиреЗ рдХреЗ рд▓рд┐рдП рдХрд┐рдпрд╛ рдЬрд╛рддрд╛ рд╣реИред
- MOV
- LOAD
- STORE
- PUSH
- POP
2. Arithmetic Instructions
Arithmetic Operations Perform рдХрд░рдиреЗ рдХреЗ рд▓рд┐рдП рдЙрдкрдпреЛрдЧ рдХреА рдЬрд╛рддреА рд╣реИрдВред
- ADD
- SUB
- MUL
- DIV
- INC
- DEC
3. Logical Instructions
Logical Operations рддрдерд╛ Comparisons рдХреЗ рд▓рд┐рдП рдЙрдкрдпреЛрдЧ рд╣реЛрддреА рд╣реИрдВред
- AND
- OR
- XOR
- NOT
- CMP
4. Branch Instructions
Program Flow рдХреЛ рдмрджрд▓рдиреЗ рдХреЗ рд▓рд┐рдП рдЙрдкрдпреЛрдЧ рдХреА рдЬрд╛рддреА рд╣реИрдВред
- JMP
- CALL
- RET
- LOOP
5. Input Output Instructions
Input рддрдерд╛ Output Devices рдХреЗ рд╕рд╛рде Communication рдХреЗ рд▓рд┐рдП рдЙрдкрдпреЛрдЧ рдХреА рдЬрд╛рддреА рд╣реИрдВред
- IN
- OUT
6. Machine Control Instructions
CPU рдХреЗ Internal Control рдХреЗ рд▓рд┐рдП рдЙрдкрдпреЛрдЧ рдХреА рдЬрд╛рддреА рд╣реИрдВред
- HLT
- NOP
- WAIT
Instruction Execution Cycle
- Fetch Instruction
- Decode Instruction
- Fetch Operand
- Execute Instruction
- Store Result
CPU Program Counter рдХреА рд╕рд╣рд╛рдпрддрд╛ рд╕реЗ Instruction Fetch рдХрд░рддрд╛ рд╣реИ рдФрд░ рдлрд┐рд░ рдЙрд╕реЗ Execute рдХрд░рддрд╛ рд╣реИред
Addressing Modes
Addressing Mode рдпрд╣ рдирд┐рд░реНрдзрд╛рд░рд┐рдд рдХрд░рддрд╛ рд╣реИ рдХрд┐ Operand рдХрд╣рд╛рдБ рд╕реНрдерд┐рдд рд╣реИред
| Addressing Mode | Description |
|---|---|
| Immediate | Data Directly Present |
| Direct | Address Specified |
| Indirect | Address Stored in Register |
| Register | Operand in Register |
Instruction Set Architecture (ISA)
Instruction Set Architecture Hardware рдФрд░ Software рдХреЗ рдмреАрдЪ Interface рдкреНрд░рджрд╛рди рдХрд░рддреА рд╣реИред ISA рдпрд╣ рдирд┐рд░реНрдзрд╛рд░рд┐рдд рдХрд░рддреА рд╣реИ рдХрд┐ Processor рдХрд┐рд╕ рдкреНрд░рдХрд╛рд░ Instructions рдХреЛ Execute рдХрд░реЗрдЧрд╛ред
- Instruction Formats
- Registers
- Addressing Modes
- Data Types
- Memory Model
RISC and CISC Instruction Sets
| Feature | RISC | CISC |
|---|---|---|
| Instructions | Simple | Complex |
| Execution Time | Fast | Moderate |
| Hardware Complexity | Low | High |
Advantages of Instruction Set
- Efficient Program Execution
- Hardware Software Compatibility
- Standardized Processing
- Improved Performance
- Easy Programming
Limitations
- Hardware Dependency
- Architecture Specific Design
- Complex Instruction Decoding
- Performance Constraints
Applications
- Microprocessors
- Embedded Systems
- Mobile Processors
- Desktop Computers
- Servers
- Supercomputers
Industrial Importance
- Processor Manufacturing
- Operating System Development
- Compiler Design
- Embedded Device Development
- Cloud Infrastructure
Viva Questions
- What is an Instruction Set?
- What is Opcode?
- What is Operand?
- What are Data Transfer Instructions?
- What are Arithmetic Instructions?
- What are Logical Instructions?
- What is ISA?
- What is Addressing Mode?
- Difference between RISC and CISC?
- What is Instruction Cycle?
Exam Oriented Important Questions
- Define Instruction Set.
- Explain Instruction Format.
- Discuss Types of Instructions.
- Explain Instruction Execution Cycle.
- What is Instruction Set Architecture?
- Differentiate between RISC and CISC.
- Explain Addressing Modes with Examples.
Conclusion
Instruction Set CPU рдХреА рдХрд╛рд░реНрдпрдХреНрд╖рдорддрд╛ рдХрд╛ рдЖрдзрд╛рд░ рд╣реИред Processor рджреНрд╡рд╛рд░рд╛ Execute рдХреА рдЬрд╛рдиреЗ рд╡рд╛рд▓реА рд╕рднреА Instructions рдЗрд╕реА Instruction Set рдХрд╛ рднрд╛рдЧ рд╣реЛрддреА рд╣реИрдВред Computer Architecture, Processor Design рддрдерд╛ Operating Systems рдХреЛ рд╕рдордЭрдиреЗ рдХреЗ рд▓рд┐рдП Instruction Set рдХрд╛ рдЕрдзреНрдпрдпрди рдЕрддреНрдпрдВрдд рдЖрд╡рд╢реНрдпрдХ рд╣реИред
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